DSP in FPGAs

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An Introduction to Field-Programmable Gate Arrays for Digital Signal Processing[edit]

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\section{What's an FPGA?}

A Field-Programmable Gate Array (FPGA) is chip for performing digital logic operations. At its most basic level, and FPGA is a bunch of simple logic elements and a huge network of wires, and connections between logic elements and wires are activated by an array of bits that is loaded onto the chip. This makes an FPGA something of a chameleon; a user can rewire the chip to do many different things, depending on the application.

The only kind of chip that competes with the FPGA for flexibility is the Central Processing Unit (CPU) that sits at the heart of every modern computer. CPUs are flexible for a completely different reason than FPGAs. CPUs are not configurable chips. Instead, they are hard-wired with a number of registers for holding numbers, and a number of supported operations for how to modify or combine the numbers in those registers. What makes a CPU flexible is its capability to execute these operations in arbitrary order, according to the instructions contained in a program in memory that was written by a user. Long ago, CPUs had only a single core and so every instruction in a program was executed sequentially, one at a time. Nowadays, CPUs have multiple cores, and several instructions can be executed in parallel. This development notwithstanding, CPUs are basically serial processors, with some parallel capability allowed by multicore technology.

In contrast, FPGAs are massively parallel. Every logic element in an FPGA is like a parallel processor. The rub, of course, is that these ``processors do very simple things, and once you configure a logic element to perform an operation, that is the only operation it can perform until the FPGA is reprogrammed. The parallel-ality of an FPGA makes it incredibly powerful for processing high-speed streaming data, but it also makes FPGAs hard to program. The difference in programming paradigms between CPUs and FPGAs is probably the biggest road-block to the widespread adoption of FPGA co-processors in computers.

\section{Clocks and Timing} \subsection{Apology/Motivation} \subsection{Timing Diagrams} \subsection{Registers} \subsection{Setup and Hold} \subsection{Latency} \subsection{Pipelining: Latency vs. Throughput}

\section{Bits, Bytes, and Beyond} \subsection{A Bit is a Wire} \subsection{Value vs. Representation} \subsection{Unsigned vs. Signed Representations} \subsection{The Binary Point}

\section{FPGA Resources} \subsection{Slices} \subsection{Block RAMs} \subsection{Multipliers/DSPs} \subsection{CPUs}

\section{Design Tools} \subsection{Verilog} \subsection{VHDL} \subsection{Graphical Design Tools}

\section{Connecting FPGAs to CPUs} \subsection{Basic Computer Architecture} Buses and Addresses \subsection{Clock Boundaries}

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