Difference between revisions of "CasperTutorial01"
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Connect the blocks as per the diagram at the beginning of this section. | Connect the blocks as per the diagram at the beginning of this section. | ||
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\section{Simulating} | \section{Simulating} | ||
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The design can be simulated with clock-for-clock accuracy directly from within | The design can be simulated with clock-for-clock accuracy directly from within | ||
Simulink. Set the number of clock cycles that you'd like to simulate and press | Simulink. Set the number of clock cycles that you'd like to simulate and press | ||
− | the play button in the top toolbar | + | the play button in the top toolbar: |
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig27.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig27.png}\end{figure} | ||
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will complete in the blink of an eye for this small design with just 10 clock | will complete in the blink of an eye for this small design with just 10 clock | ||
cycles. | cycles. | ||
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You can double-click on the scopes to see what the signals look like on those | You can double-click on the scopes to see what the signals look like on those | ||
− | lines. For example, the one connected to the counter should look like | + | lines. For example, the one connected to the counter should look like: |
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig28.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig28.png}\end{figure} | ||
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\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig29.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig29.png}\end{figure} | ||
− | Once you have verified that | + | Once you have verified that the design functions as you'd like, you're ready |
− | to compile for the FPGA. | + | to compile for the FPGA. |
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\section{Compiling} | \section{Compiling} | ||
− | + | You have constructed essentially three completely separate little instruments. | |
− | + | There is a flashing LED, a counter you can start/stop/reset from software, | |
− | and | + | and an adder. These components are driven by the same 100MHz clock, but they operate independently. |
− | clock | ||
− | In order to compile this to an FPGA bitstream, type bee\_xps on the Matlab | + | In order to compile this to an FPGA bitstream, type "bee\_xps" on the Matlab |
− | command line. Leave all options on defaults. Ensure that the listed design is | + | command line. Leave all options on defaults. Ensure that the listed design under System Generator Design Name is |
− | the one you want to compile | + | the one you want to compile. If it is not, click |
− | anywhere on your design | + | anywhere on your design (making it the highlighted window), then click gcs (for Get Current System). |
− | To start the process, | + | To start the process, click "RUN XPS": |
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig30.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig30.png}\end{figure} | ||
− | Compile time | + | Compile time will vary by computer (on the computer we tried, it took 15 minutes). When |
− | complete, you should | + | complete, you should see a popup box: |
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig31.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig31.png}\end{figure} | ||
− | \section{Transferring | + | |
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+ | \section{Transferring the Bitstream to ROACH} | ||
If you navigate to the directory containing your *.mdl file, you | If you navigate to the directory containing your *.mdl file, you | ||
− | will find a | + | will find a directory with the same name as your Simulink design. |
− | + | In that directory, you will find another directory "bit\_files" that holds your bitstreams. | |
− | two files with names of the form | + | There should be two files with names of the form |
<design\_name>\_<start\_compile\_time>.XXX. | <design\_name>\_<start\_compile\_time>.XXX. | ||
− | The *.bit is the raw FPGA bitstream that | + | The *.bit is the raw FPGA bitstream that can be manually loaded using a Xilinx |
− | JTAG programmer. | + | JTAG programmer. Instead, we'll opt to use the *.bof file--a BORPH |
− | executable. | + | executable. Let's transfer this file to your ROACH board now. |
To transfer files to ROACH, you can use any program capable of doing Secure Copy over SSH | To transfer files to ROACH, you can use any program capable of doing Secure Copy over SSH | ||
Protocol (SCP) transfers. On Linux, scp is the standard tool. | Protocol (SCP) transfers. On Linux, scp is the standard tool. | ||
+ | You will need to place your *.bof file in the /boffiles directory of the ROACH filesystem, and make it executable. | ||
+ | If your ROACH is configured to have its own file system and you are running Linux, this may be as simple as: | ||
+ | \begin{verbatim} | ||
+ | bash$ scp *.bof root@<roach-ip>:/boffiles | ||
+ | bash$ ssh root@<roach-ip> | ||
+ | root@roach020112:~# chmod a+x /boffiles/*.bof | ||
+ | \end{verbatim} | ||
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\section{Connecting to your ROACH board} | \section{Connecting to your ROACH board} | ||
− | \subsection{ | + | \subsection{Boot the ROACH} |
− | + | If you want to watch ROACH boot, you need to connect to it using a serial port. Under Linux, minicom is | |
a standard tool for communicating over the serial port. On Windows, try HyperTerminal. | a standard tool for communicating over the serial port. On Windows, try HyperTerminal. | ||
Set the serial connection to use your serial port (usually of the form /dev/tty* on Linux or | Set the serial connection to use your serial port (usually of the form /dev/tty* on Linux or | ||
com1 on Windows) at 115200 baud, 8N1 with no flow control. | com1 on Windows) at 115200 baud, 8N1 with no flow control. | ||
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You will be greeted with a printout similar to this one: | You will be greeted with a printout similar to this one: | ||
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\end{verbatim} | \end{verbatim} | ||
− | This is ROACH's version of a BIOS along with some basic | + | This is ROACH's version of a BIOS along with some basic CPU health printouts. |
Press any key here to stop the automatic boot process. This is the state of the | Press any key here to stop the automatic boot process. This is the state of the | ||
ROACH boards when shipping. You can configure it differently should you please. | ROACH boards when shipping. You can configure it differently should you please. | ||
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where to find the filesystem. | where to find the filesystem. | ||
− | After Linux has completed its boot process, you will be greeted with a Debian prompt. | + | After Linux has completed its boot process, you will be greeted with a Debian Linux prompt. |
\begin{verbatim} | \begin{verbatim} | ||
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roach020112 login: | roach020112 login: | ||
\end{verbatim} | \end{verbatim} | ||
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+ | \subsection{SSH into ROACH} | ||
You can connect to your ROACH board by SSHing directly into it. Under Linux, use the command "ssh". | You can connect to your ROACH board by SSHing directly into it. Under Linux, use the command "ssh". | ||
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We are now ready to start working with the ROACH board. | We are now ready to start working with the ROACH board. | ||
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\section{Communicating directly using BORPH} | \section{Communicating directly using BORPH} |