# Difference between revisions of "CasperTutorial01"

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To demonstrate some simple mathematical operations, we will create an adder. It | To demonstrate some simple mathematical operations, we will create an adder. It | ||

− | will add two | + | will add numbers in two CPU-controllable registers and output the result to another software |

− | register. | + | register. As will be the case for most DSP in FPGAs, this adder will use fixed-point (integer) |

− | + | data types. | |

− | We will calculate a+b=sum\_a\_b. | + | We will calculate $a+b=sum\_a\_b$. |

\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig23.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig23.png}\end{figure} | ||

− | \subsubsection{Add | + | \subsubsection{Add Three Software Registers } |

− | Add two more input | + | Add two more input {\bf Software Registers} to specify the |

− | numbers to add | + | numbers to add, and one more output {\bf Software Register} for returning the sum. |

− | + | You may either copy your existing software register blocks or drag them in from the {\it BEE\_XPS Blockset} library. | |

− | + | Set the I/O direction to "From Processor" on the first two, and "To Processor" on the | |

− | |||

− | direction to From Processor on the first two and | ||

third one. | third one. | ||

− | \subsubsection{Add | + | \subsubsection{Add an AddSub Block} |

− | + | Drag into your design the adder/subtractor block: {\it Xilinx Blockset $\rightarrow$ Math | |

− | $\rightarrow$ AddSub | + | $\rightarrow$ AddSub}. This block can |

− | perform addition or subtraction. | + | perform addition or subtraction. Its default configuration is for addition, and we'll leave that way: |

− | addition | ||

\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig24.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig24.png}\end{figure} | ||

− | The | + | Now we have an interesting problem. The two input registers are 32 bits wide, and when we add them, we need 33 bits to guarantee that we can hold the full sum. However, our output register has only 32 bits. |

− | |||

There are a number of ways of fixing this: | There are a number of ways of fixing this: | ||

\begin{itemize} | \begin{itemize} | ||

\item limit the input bitwidth(s) with slice blocks | \item limit the input bitwidth(s) with slice blocks | ||

− | \item limit the output bitwidth with slice blocks | + | \item limit the output bitwidth with slice blocks, accepting that the sum may overflow and wrap |

− | \item | + | \item saturate the sum at the maximum/minimum values that can be represented with 32 bits. |

\end{itemize} | \end{itemize} | ||

Since you have already seen slice blocks demonstrated, let's try to set the | Since you have already seen slice blocks demonstrated, let's try to set the | ||

− | AddSub block to be a 32 bit saturating adder. On the second tab, set it for | + | AddSub block to be a 32-bit saturating adder. On the second tab, set it for |

− | user-defined precision, unsigned 32 bits. | + | user-defined precision, unsigned 32 bits. Change overflow to "saturate": |

− | |||

− | |||

− | |||

\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig25.png}\end{figure} | \begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig25.png}\end{figure} | ||

− | + | Now, when the sum exceeds the maximum value that can be represented with 32 bits, this adder will return $2^{32} -1$. | |

− | + | \subsubsection{Add a Scope and Constants} | |

− | |||

− | |||

− | \ | + | Add a {\bf Scope} and two {\bf Constant}. The constants are for simulation; set the values to anything you like. |

− | + | \subsubsection{Wire the Blocks} | |

− | + | Connect the blocks as per the diagram at the beginning of this section. | |

\section{Simulating} | \section{Simulating} |