Difference between revisions of "CasperTutorial01"

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Start Matlab and open Simulink (type "simulink"
 
Start Matlab and open Simulink (type "simulink"
on the Matlab command line).  Start a new model file by following Simulink Library Browser $\rightarrow$ File $\rightarrow$ New $\rightarrow$ Model:
+
on the Matlab command line).  Start a new model file by following {\it Simulink Library Browser $\rightarrow$ File $\rightarrow$ New $\rightarrow$ Model}:
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig2.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig2.png}\end{figure}
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All CASPER designs must have two blocks: a {\bf System Generator} and an {\bf XPS Core Config}.
 
All CASPER designs must have two blocks: a {\bf System Generator} and an {\bf XPS Core Config}.
Go to Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements and drag a {\bf System Generator} block onto your new model:
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Go to {\it Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements} and drag a {\bf System Generator} block onto your new model:
 
   
 
   
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
  
 
You should not configure the {\bf System Generator} block directly; add an  
 
You should not configure the {\bf System Generator} block directly; add an  
{\bf XSG Core Config} block from Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset to do it for you:
+
{\bf XSG Core Config} block from {\it Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset} to do it for you:
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
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\subsubsection{Add a Counter}
 
\subsubsection{Add a Counter}
  
Drag a {\bf Counter} into your design from Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements.  Double-click it and set the parameters for a
+
Drag a {\bf Counter} into your design from {\it Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements}.  Double-click it and set the parameters for a
 
free-running, 27-bit, unsigned counter:
 
free-running, 27-bit, unsigned counter:
  
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To select the most significant bit (MSB) of the counter, we need to add a  
 
To select the most significant bit (MSB) of the counter, we need to add a  
{\bf Slice} block to your model from Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic
+
{\bf Slice} block to your model from {\it Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic
Elements.
+
Elements}.
  
 
Double-click on the newly added slice block. There are multiple ways to select
 
Double-click on the newly added slice block. There are multiple ways to select
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\subsubsection{Add a GPIO}
 
\subsubsection{Add a GPIO}
  
Drag in a {\bf gpio} (General Purpose Input/Output) block from Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset.  This block is used to interface your Simulink design to specific pins on the FPGA chip.
+
Drag in a {\bf gpio} (General Purpose Input/Output) block from {\it Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset}.  This block is used to interface your Simulink design to specific pins on the FPGA chip.
 
Set it to use ROACH's LED bank as output with GPIO bit index 0 (i.e. the first LED):
 
Set it to use ROACH's LED bank as output with GPIO bit index 0 (i.e. the first LED):
  
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\subsubsection{Add a Terminator}
 
\subsubsection{Add a Terminator}
  
This is optional, but to prevent warnings about unconnected outputs, you can connect unused outputs to a {\bf Terminator} block from Simulink Library Browser $\rightarrow$ Simulink $\rightarrow$ Sinks:  
+
This isn't strictly required, but to prevent warnings about unconnected outputs, you can connect unused outputs to a {\bf Terminator} block from {\it Simulink Library Browser $\rightarrow$ Simulink $\rightarrow$ Sinks}:  
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig12.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig12.png}\end{figure}
  
Only Xilinx blocks (blue with an "X" logo, from Simulink Library Browser $\rightarrow$ Xilinx Blockset) compile to hardware. Blocks from the Simulink Library Browser $\rightarrow$ Simulink library are usually white, and they never compile into hardware; they are for simulation only.  These blocks are not to be confused with {\bf Subsystems}, which can appear as white blocks, but are hierarchical elements that contain other blocks, including Xilinx blocks that compile to hardware.
+
Only Xilinx blocks (blue with an "X" logo, from {\it Simulink Library Browser $\rightarrow$ Xilinx Blockset}) compile to hardware. Blocks from the {\it Simulink Library Browser $\rightarrow$ Simulink} library are usually white, and they never compile into hardware; they are for simulation only.  These blocks are not to be confused with {\bf Subsystems}, which can appear as white blocks, but are hierarchical elements that contain other blocks, including blocks that compile to hardware.
  
Blocks from the Xilinx Blockset library use a different data type than the rest of Simulink.  For this reason, you need to use yellow {\bf Gateway} blocks (from Simulink Library Browser $\rightarrow$ Xilinx Blockset) whenever connecting them to other  
+
Blocks from the {\it Xilinx Blockset} library use a different data type than the rest of Simulink.  For this reason, you need to use yellow {\bf Gateway} blocks (from {\it Simulink Library Browser $\rightarrow$ Xilinx Blockset}) whenever connecting them to other  
 
Simulink-provided, simulation-only blocks.  Many of
 
Simulink-provided, simulation-only blocks.  Many of
the yellow blocks in the BEE\_XPS System Blockset, like the GPIO block, do this for you with "sim\_in" and
+
the yellow blocks in the {\it BEE\_XPS System Blockset}, like the GPIO block, do this for you with "sim\_in" and
 
"sim\_out" ports. We will see later how to use a {\bf Scope} block to monitor lines.
 
"sim\_out" ports. We will see later how to use a {\bf Scope} block to monitor lines.
  
 
\subsubsection{Connecting the Blocks Together}
 
\subsubsection{Connecting the Blocks Together}
  
It is a good idea to rename your blocks to something more sensible, like
+
Draw wires between blocks by clicking on the output of a block and dragging the line over to the input of another block.  You may want to refer to the figure at the beginning of this section to remember how they should look wired up.
counter\_led instead of just counter. Do this simply by double-clicking on the
 
name of the block and editing the text appropriately.
 
  
It is a good time to save this new design. There are some Matlab limitations you should be aware-of:
+
It is good practice to rename your blocks to something descriptive, like
+
"counter\_led", instead of just "counter". Do this by double-clicking on the
Do not use spaces in your filenames, or anywhere in the file path as it will break the toolflow.
+
name of the block and editing the text.
  
Total path length cannot be more than 64 characters. By "path", I am refering
+
Now would also be a good time to save this new design. There are some Matlab limitations you should be aware-of.
to not only the file path, but also the path to any block within your design.
+
Do not use spaces in the names of your Matlab files, or in any of the directories upstream in your path, as it will break the toolflow.
For example, if you save this file to c:\verb=\=projects\verb=\=myfile.mdl, the
+
Inside Simulink, names cannot be more than 64 characters. Some low-level interface blocks will be automatically renamed to include your filename, any hierarchical subsystems containing the block, and its own name.  
 +
For example, if you save this file under Windows to c:\verb=\=projects\verb=\=myfile.mdl, the
 
longest Matlab-indexed path would be
 
longest Matlab-indexed path would be
c:\verb=\=projects\verb=\=myfile.mdl\verb=\=counter\_led. While this is quite
+
c:\verb=\=projects\verb=\=myfile.mdl\verb=\=counter\_led. To avoid running against the 64-character limitation, try to keep your names concise but meaningful.
short, but there can be additional blocks hidden underneath some of your top
 
level blocks. This is the case with GPIO, for example. This will become clearer
 
later when we demonstrate the use of SubSystems. For now, try to keep your
 
names short.
 
  
Please save your design in c:\verb=\=projects\verb=\=<YOUR\_INITIALS>\_tut1.mdl.
+
\subsection{Controlling a Counter from Software}
  
 
+
In this section, we will demonstrate the use of special {\bf Software Register} blocks that can be accessed both from the FPGA and from an on-board Central Processing Unit (CPU) running Linux.  With these blocks, we will implement a counter that can be started, stopped, reset, and read out from software:
\subsection{Software control}
 
 
 
To demonstrate the use of software registers and control of the FPGA through
 
the PPC, we will add a controllable counter to the above design. The counter
 
can be started and stopped from software and also reset. We will be able to
 
monitor the counter's current value too.
 
 
 
By the end of this section, you will create a system that looks like this:
 
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig14.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig14.png}\end{figure}
  
\subsubsection{Add the software registers }
+
\subsubsection{Add Software Registers}
 
 
We need two software registers. One to control the counter, and a second one to
 
read its current value. From the BEE\_XPS System Blockset library, drag two
 
Software Registers onto your design.
 
  
Set the I/O direction to From Processor on the first one to enable dataflow from PowerPC to the FPGA fabric. Set it to To Processor on the second one.
+
We need two {\bf Software Registers} from {\it Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset}: one to control the counter, and a second one to
 +
read its current value.
 +
On the first one, set the I/O direction to "From Processor" so that its value is controlled from the CPU.
 +
On the second, set the I/O direction to "To Processor" to allow the FPGA to set the value:
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig16.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig16.png}\end{figure}
  
Note the field Data bitwidth is greyed out with a value 32. This is because all software registers have a fixed data bitwidth of 32 bits.
+
Note how "Data bitwidth" is greyed out with a value 32. All {\bf Software Registers} have a bitwidth fixed to 32 to match the width of the bus connecting them to the CPU.
  
Rename the registers to something sensible, as these names are mapped to
+
The names of these {\bf Software Registers} are mapped to the names of
filenames in the PPC for controlling the design. Avoid using spaces, slashes
+
files on the CPU that you will use to access values. Avoid using spaces, slashes
and other funny characters in these names (spaces automatically get remapped to
+
and other funny characters in these names.  Spaces will be automatically remapped to
underscores anyway, but should be avoided for clarity). I suggest counter\_ctrl
+
underscores, but for clarity, we will avoid that for now. Let's use "counter\_ctrl"
and counter\_value, to represent the control and output registers respectively.
+
and "counter\_value" to represent the control and output registers, respectively.
  
 
Also note that the software registers have sim\_in and sim\_out ports. The
 
Also note that the software registers have sim\_in and sim\_out ports. The

Revision as of 11:37, 26 March 2010