Difference between revisions of "CasperTutorial01"

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\subsubsection{Add Xilinx System Generator and XSG Core Config blocks}
 
\subsubsection{Add Xilinx System Generator and XSG Core Config blocks}
  
All CASPER designs must have two blocks: a System Generator and an XPS Core Config.
+
All CASPER designs must have two blocks: a {\bf System Generator} and an {\bf XPS Core Config}.
 +
Go to Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements and drag a {\bf System Generator} block onto your new model:
 +
 +
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
  
Go to Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements and drag a System Generator
+
You should not configure the {\bf System Generator} block directly; add an  
block onto your new model. You should not configure this block directly; add an  
+
{\bf XSG Core Config} block from Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset to do it for you:
XSG Core Config block from Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset to do it for you:
 
  
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
+
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
  
 
All hardware-related (possibly board-specific) blocks are yellow and can be found in this BEE\_XPS
 
All hardware-related (possibly board-specific) blocks are yellow and can be found in this BEE\_XPS
 
library. Blocks relating to Digital Signal Processing (DSP) are found in the CASPER DSP library and have other colors.
 
library. Blocks relating to Digital Signal Processing (DSP) are found in the CASPER DSP library and have other colors.
  
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
+
Double click on the XSG core config block that you just added. Set it for
 +
"ROACH: SX95t" with "sys\_clk" as the clock source:
  
Double click on the XSG core config block that you just added. Set it for
+
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig5.png}\end{figure}
ROACH: SX95t with sys\_clk as the clock source. sys\_clk is an on-board 100MHz
 
crystal oscillator. Click OK. This will go off and configure the System Generator block which you previously
 
added.
 
  
 
For the curious, the available clocking options include:
 
For the curious, the available clocking options include:
 
\begin{itemize}
 
\begin{itemize}
     \item sys\_clk: use onboard 100MHz crystal connected to the FPGA
+
     \item sys\_clk: use on-board 100MHz crystal connected to the FPGA
 
     \item sys\_clk2x: use frequency-doubled version of sys\_clk generated using a Phase Locked Loop (PLL) set by a Digital Clock Manager (DCM) on the FPGA
 
     \item sys\_clk2x: use frequency-doubled version of sys\_clk generated using a Phase Locked Loop (PLL) set by a Digital Clock Manager (DCM) on the FPGA
 
     \item arb\_clk: use clock generated from sys\_clk using a DCM (rounded to nearest integer within range of DCM's abilities)
 
     \item arb\_clk: use clock generated from sys\_clk using a DCM (rounded to nearest integer within range of DCM's abilities)
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\end{itemize}
 
\end{itemize}
  
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig5.png}\end{figure}
+
\subsection{Flashing an LED}
  
\subsection{Flashing LED}
+
To demonstrate the basic use of hardware interfaces, we will implement a flashing LED by adding the following circuitry to our model:
  
To demonstrate the basic use of hardware interfaces, we will add a flashing LED.
+
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig13.png}\end{figure}
With the FPGA running at 100MHz, the most significant bit (msb) of a 27 bit
 
counter will toggle every 0.745 seconds. We can output this bit to an LED on
 
ROACH. ROACH has four green LEDs. We will now connect a counter to the first
 
one.
 
  
\subsubsection{Add a counter}
+
With the FPGA running at 100MHz, the most significant bit (msb) of a 27-bit
 +
counter will toggle every 0.745 seconds. We can output this bit to one of the four
 +
green LEDs on the
 +
ROACH.
  
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig6.png}\end{figure}
+
\subsubsection{Add a Counter}
  
Add a counter to your design by navigating to Xilinx Blockset $\rightarrow$ Basic Elements
+
Drag a {\bf Counter} into your design from Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic Elements.  Double-click it and set the parameters for a
$\rightarrow$ Counter and dragging it onto your model.  Double-click it and set it for
+
free-running, 27-bit, unsigned counter:
free running, 27 bits, unsigned.
 
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig7.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig7.png}\end{figure}
  
\subsubsection{Add a slice block to select out the msb}
+
\subsubsection{Add a Slice}
  
We now need to select the most significant bit of the counter. We do this using
+
To select the most significant bit (MSB) of the counter, we need to add a
a slice block, which Xilinx provides. Xilinx Blockset $\rightarrow$ Basic
+
{\bf Slice} block to your model from Simulink Library Browser $\rightarrow$ Xilinx Blockset $\rightarrow$ Basic
Elements $\rightarrow$ Slice.
+
Elements.
  
 
Double-click on the newly added slice block. There are multiple ways to select
 
Double-click on the newly added slice block. There are multiple ways to select
which bit(s) you want.  In this case, I find it simplest to index from the
+
which bit(s) you want.  In this case, it is simplest to index from the
upper end and select the first bit. If you wanted the lsb, you could also index
+
upper end (MSB) and select the first bit. Set your slice to be 1 bit wide with 0 offset from the top bit:
from the lsb,. You can either select the width and offset, or two bit
 
locations.
 
 
 
Set it for 1 bit wide with offset from top bit at zero.
 
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig9.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig9.png}\end{figure}
  
\subsubsection{Add a GPIO block }
+
You could also have indexed
 +
from the least significant bit (LSB) with an offset of 26.
  
(BEE\_XPS library $\rightarrow$ gpio).
+
\subsubsection{Add a GPIO}
  
Set it to use ROACH's LED bank as output, GPIO bit index 0 (the first LED).
+
Drag in a {\bf gpio} (General Purpose Input/Output) block from Simulink Library Browser $\rightarrow$ BEE\_XPS System Blockset.  This block is used to interface your Simulink design to specific pins on the FPGA chip.
 +
Set it to use ROACH's LED bank as output with GPIO bit index 0 (i.e. the first LED):
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig11.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig11.png}\end{figure}
  
\subsubsection{Add a terminator}
+
\subsubsection{Add a Terminator}
  
To prevent warnings about unconnected outputs, terminate all unused outputs using a Terminator:  
+
This is optional, but to prevent warnings about unconnected outputs, you can connect unused outputs to a {\bf Terminator} block from Simulink Library Browser $\rightarrow$ Simulink $\rightarrow$ Sinks:  
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig12.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig12.png}\end{figure}
  
Note that all blocks from the "Simulink" library (usually white), will not be
+
Only Xilinx blocks (blue with an "X" logo, from Simulink Library Browser $\rightarrow$ Xilinx Blockset) compile to hardware. Blocks from the Simulink Library Browser $\rightarrow$ Simulink library are usually white, and they never compile into hardware; they are for simulation only. These blocks are not to be confused with {\bf Subsystems}, which can appear as white blocks, but are hierarchical elements that contain other blocks, including Xilinx blocks that compile to hardware.
compiled into hardware. They are present for simulation only and expect
 
continuous signals, not discreet.
 
 
 
Only Xilinx blocks (they are blue with Xilinx logo) will be compiled to hardware.
 
  
For this reason, you need to use gateway blocks whenever connecting a
+
Blocks from the Xilinx Blockset library use a different data type than the rest of Simulink.  For this reason, you need to use yellow {\bf Gateway} blocks (from Simulink Library Browser $\rightarrow$ Xilinx Blockset) whenever connecting them to other
Simulink-provided block (like a scope or constant) for simulationsSome of
+
Simulink-provided, simulation-only blocksMany of
the CASPER blocks (like the GPIO block) do this for you with "sim\_in" and
+
the yellow blocks in the BEE\_XPS System Blockset, like the GPIO block, do this for you with "sim\_in" and
"sim\_out". We will see later how to use a 'scope to monitor these lines.
+
"sim\_out" ports. We will see later how to use a {\bf Scope} block to monitor lines.
  
\subsubsection{Connect your design}
+
\subsubsection{Connecting the Blocks Together}
  
 
It is a good idea to rename your blocks to something more sensible, like
 
It is a good idea to rename your blocks to something more sensible, like
 
counter\_led instead of just counter. Do this simply by double-clicking on the
 
counter\_led instead of just counter. Do this simply by double-clicking on the
 
name of the block and editing the text appropriately.
 
name of the block and editing the text appropriately.
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig13.png}\end{figure}
 
  
 
It is a good time to save this new design. There are some Matlab limitations you should be aware-of:
 
It is a good time to save this new design. There are some Matlab limitations you should be aware-of:

Revision as of 10:56, 26 March 2010