Difference between revisions of "CasperTutorial01"

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\section{Introduction}
 
\section{Introduction}
  
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In this tutorial, you will create a simple Simulink design using both standard
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In this tutorial, you will create a simple Simulink design using the standard
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Xilinx System Generator blockset, as well as library blocks specific to ROACH.
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Xilinx System Generator blockset and library blocks specific to ROACH.
 
At the end of this tutorial, you will have a BORPH executable file (a BOF file)
 
At the end of this tutorial, you will have a BORPH executable file (a BOF file)
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and you will know how to interact with your running hardware design using
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and you will know how to interact with a ROACH board your running hardware design using
 
BORPH.
 
BORPH.
  
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\section{Setup}
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\section{Creating Your Design}
  
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The lab at the workshop is preconfigured with the CASPER libraries, Matlab and
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Create a new model: Start Matlab and open Simulink (by typing simulink
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Xilinx tools. Simply double-click the mlib\_devel\_10\_1 icon on the desktop to
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on the Matlab command line).
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start Matlab with all required libraries.
 
  
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\section{Creating Your Design}
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\subsection{Create a new model}
  
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Create a new model: Start Matlab and open Simulink (either by typing simulink
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\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig2.png}\end{figure}
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on the Matlab command line, or by click in the Simulink icon in the taskbar).
 
  
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\subsection{Create a new model:}
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\subsubsection{Add Xilinx System Generator and XSG Core Config blocks}
  
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\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig2.png}\end{figure}
 
  
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\subsubsection{Add Xilinx System Generator and XSG core config blocks:}
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All CASPER designs must have two blocks: a System Generator and an XSP Core Config.
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig3.png}\end{figure}
  
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Add a System Generator block from the Xilinx library by locating the Xilinx
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Locate the Xilinx
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Blockset library's Basic Elements subsection and dragging a System Generator
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Blockset Library's Basic Elements subsection and drag a System Generator
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token onto your new file. Do not configure it directly, but rather add an XSG
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token onto your new file. You should not configure this block directly; the XSG
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core config from the BEE XPS System Blockset library to do this for you:
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core config from the BEE XPS System Blockset library to do it for you:
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig4.png}\end{figure}
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library. This library contains all the board-specific components colloquially
 
library. This library contains all the board-specific components colloquially
 
called Yellow Blocks.
 
called Yellow Blocks.
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DSP blocks are found in the CASPER DSP library and have other colors.
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DSP related blocks are found in the CASPER DSP library and have other colours.
 
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Tutorial 3 will introduce you to these blocks.
 
  
 
Double click on the XSG core config block that you just added. Set it for
 
Double click on the XSG core config block that you just added. Set it for
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ROACH: SX95t with sys\_clk as the clock source. sys\_clk is an onboard 100MHz
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ROACH: SX95t with sys\_clk as the clock source. sys\_clk is an on-board 100MHz
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crystal.   
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crystal oscillator.  Click OK. This will go off and configure the System Generator block which you previously
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added.
  
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Leave everything else defaults and click OK.
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For the curious, the available clocking options include:
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Clocking options include:
 
 
\begin{itemize}
 
\begin{itemize}
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     \item sys\_clk: This is an onboard 100MHz crystal which is connected to the FPGA.
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     \item sys\_clk: use onboard 100MHz crystal connected to the FPGA
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     \item sys\_clk2x: This is the same sys\_clk souce (100MHz onboard crystal), PLL'd up to 200MHz using a Digital Clock Manager (DCM) in the FPGA.
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     \item sys\_clk2x: use frequency-doubled version of sys\_clk generated using a Phase Locked Loop (PLL) set by a Digital Clock Manager (DCM) on the FPGA
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     \item arb\_clk: Arbitrary clock using 100MHz onboard crystal with DCM on FPGA to produce any frequency (rounded to nearest available integer n/m in accordance with DCM abilities).
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     \item arb\_clk: use clock generated from sys\_clk using a DCM (rounded to nearest integer within range of DCM's abilities)
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     \item aux\_clk (usr\_clk on older platforms): SMA input to board. PLL'd versions of these clocks are also available.
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     \item aux\_clk (a.k.a. usr\_clk): use external clock input to board through SMA connector. PLL'd versions also available
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     \item adcX\_clk: For use in conjuction with ADC boards, clock the FPGA off the ADC. For iADC and KATADC, this is 1/4 of sampling rate (ADCs demux internally). You need to use one of these clocks if you are using an ADC.
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     \item adcX\_clk: use sample clock from attached ADC board. For some ADCs (iADC, KATADC), this is 1/4 of sampling rate. You need to use this option if you are using an ADC
 
\end{itemize}
 
\end{itemize}
  
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig5.png}\end{figure}
 
\begin{figure}[h!]\centering\includegraphics[scale=.5]{tut1_fig5.png}\end{figure}
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This will go off and configure the System Generator block which you previously
 
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added.
 
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You need to add these two blocks for all CASPER designs.
 
  
 
\subsection{Flashing LED}
 
\subsection{Flashing LED}
  
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To demonstrate the basic use of hardware interfaces, we will make an LED flash.
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To demonstrate the basic use of hardware interfaces, we will add a flashing LED.
 
With the FPGA running at 100MHz, the most significant bit (msb) of a 27 bit
 
With the FPGA running at 100MHz, the most significant bit (msb) of a 27 bit
 
counter will toggle every 0.745 seconds. We can output this bit to an LED on
 
counter will toggle every 0.745 seconds. We can output this bit to an LED on

Revision as of 16:47, 25 March 2010

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